IEEE-EPS Distinguished Lecture by John Lau

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Lateral Communication between Chiplets (Bridges) for Heterogeneous Integration

John H Lau

Unimicron Technology Corporation
Chiplet design and heterogeneous integration packaging have been generated lots of tractions lately. For the next few years, we will see more implementations of a higher level of chiplet designs and heterogeneous integration packaging, whether it is for cost, time-to-market, performance, form factor, or power consumption. In this lecture, the following topics will be covered.

  • System-on-Chip (SoC)
  • Chiplet Design and Heterogeneous Integration Packaging – Chip Partition and Chip Split
    • Chip partition and Heterogeneous Integration
    • Chip split and Heterogeneous Integration
    • Advantages and Disadvantages
  • Lateral Communication between Chiplets (e.g., Bridges)
    • Bridge Embedded in Build-up Package Substrate
    • Bridge Embedded in Fan-Out EMC with RDLs
    • UCIe
    • Hybrid Bonding Bridge with C4 Bumps on Package Substrate
    • Hybrid Bonding Bridge with C4 Bumps on Chiplet Wafer
  • Chiplet Design and Heterogeneous Integration Packaging – Multiple System and Heterogeneous Integration
    • Multiple System and Heterogeneous Integration on Package Substrate (2D IC Integration)
    • Multiple System and Heterogeneous Integration on Package Substrate with Thin Film layer (2.1D IC Integration)
    • Multiple System and Heterogeneous Integration on TSV-less (Organic) Interposer (2.3D IC Integration)
    • Multiple System and Heterogeneous Integration on Passive TSV-Interposer (2.5D IC Integration)
    • Multiple System and Heterogeneous Integration on Active TSV-Interposer (3D IC Integration)
  • Potential R&D Topics in Chiplet Design and Heterogeneous Integration Packaging

 

Lecturer Bio

John H Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging, has published more than 515 peer-reviewed papers (375 are the principal investigator), 40 issued and pending US patents (25 are the principal inventor), and 23 textbooks (all are the first author), e.g., Chiplet Design and Heterogeneous Integration Packaging (Springer, 2023). John is an Fellow of IEEE, ASME, and IMAPS, and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share. He received many awards, e.g., the IEEE Components Packaging and Manufacturing Technology Field Award and ASME Worcester Reed Warner Medal.